In the art of testing VLSI multi-chip packages, including the chips mounted thereon, it is desirable to do so without expensive test equipment and without spending inordinate amounts of main frame computer time generating multitudes of test patterns. The application of these test patterns ultimately consumes large amounts of tester time, thus adversely affecting the tester throughput. It is also desirable to be able to easily isolate a chip or group of chips under test and diagnose the presence of a defective VLSI chip after mounting these chips on a multi-chip package. Furthermore, it is desirable for a multi-chip package to be self-testable in the field.
Major testing methods used for state of the art testing are Chip-in-Place testing as described in U.S. Pat. No. 4,220,917; Through-The-Pins testing as described in the IBM TDB, Vol. 23, No. 2, July 1980, pp. 607-609; Electronic-Chip-In-Place testing (ECIPT), as described in U.S. Pat. Nos.: 4,494,066 and 4,441,075 and Self-Test techniques, as described in U.S. Pat. Nos.: 3,614,608, 3,719,885 4,519,078 and 3,976,864, as well as many published articles in the technical literature; (see, e.g., the November 1984 issue of IEEE Design and Test entitled, "LOCST: A Built-in Self-test Technique" by LeBlanc, Johnny J.)
Testing by Chip-In-Place testing (CIPT), comprises the testing of each chip contained in a high circuit density packaging structure (without disconnecting the chip to be tested from the high circuit density packaging structure), and requires an array of precisely positioned exposed contact pads (also termed "Engineering Change Pads") for each chip contained and interconnected in the high circuit density packaging structure. The array of precisely positioned exposed contact pads for each chip is utilized by a mechanical test probe head in the testing of each chip. By electrically activating and deactivating one chip at a time, the testing of a high density packaging structure is reduced to the testing of a sequence of individual chips. This method of testing has the disadvantage of requiring a tester and the alignment and subsequent stepping of the probe over the surface of the package and by the necessity of storing and retrieving pertinent test data for each chip to and from computer memory. Moreover, performing self-test and diagnostics in the field is not possible using this method.
A further disadvantage is the poor throughput at the tester, since each chip requires individual sequential testing. Because of the increasing complexity of the logic in high density packaging structures, the testing of chips on a high density packaging structure has become increasingly complex. In order to adequately test such packaging structures, a structured logic design also known as "Design For Testability" is frequently incorporated. The absence of such a structured logic design complicates the task of generating a set of test patterns that will provide an adequate test of multi-chip module. Several approaches to this structured logic design are known in the state of the art, a common structured logic design being LSSD (Level Sensitive Scan Design).
A common thrust of the LSSD approach is to prescribe a built-in test capability for every VLSI unit, such as a chip, module etc., whereby the entire logic state of the unit under test, can be explicitly set and/or examined through exercising certain input/output (I/O) procedures at a limited number of I/O terminals. U.S. Pat. Nos. 3,761,695 entitled "Method of Level Sensitive Testing A Functional Logic System" granted Sept. 25, 1973 to E. B. Eichelberger; and 3,784,907 entitled "Method of Propagation Delay Testing A Functional Logic System" granted Jan. 8, 1974 to E. B. Eichelberger. Stated briefly, the LSSD approach comprises a test operation wherein certain desired logic test patterns are serially inputted and shifted to the appropriate latch locations when the unit is operated in the "shift mode" (i.e., by withholding the system clock excitations and turning on the shifting clock to the unit). When this is done, the latch states will provide the desired stimuli for the testing of the related logic nets. Next, the test patterns are propagated through the nets by executing one or more steps of the "Function Mode" operation (i.e., by exercising one or more system clock excitations). The response pattern of the logic networks to the applied stimuli is captured by the system latches, in a known manner depending on certain details of hardware design, often replacing the original inputted test patterns. Then, the system reverts to the shift-mode operation, outputting the response patterns for examination and comparison with standard patterns which should be present if the circuitry has operated properly. The LSSD technique is employed to design and test the component chips of the package as well as the design and test of the package. The technique logically partitions the dense LSSD logic into portions which are bounded on the inputs and outputs by Shift Register Latches (SRL's) and package pins wherever system logic dictates. Tests are then generated individually for each partition and subsequently applied through the pins of the package at the tester, as described in the Through-The-Pins Test mechanism. The limitations of the partitioning technique are (a) the partition size can exceed the capacity of available LSSD test generators, (b) the turnaround time to generate package tests is excessive, and (c) the turnaround time to regenerate package tests due to an engineering change is also excessive.
Electronic-Chip-in-Place Testing (ECIPT), provides for a design approach and testing method which allows testing of each individual chip of a plurality of interconnected chips through the module pins without physically disconnecting the chip under test. The ECIPT method permits the reapplication of chip test data at higher levels of packaging. The use of ECIPT (Electronic-Chip-In-Place-Testing) for chip isolation and testing is well known to the state of the art. This methodology is commonly used in two versions known as: Half-ECIPT and Full-ECIPT. The difference between them depends on whether only the off-chip drivers of the primary outputs of a chip are tied to an L1/L2 pair (also known as master-slave latch pair) or both the drivers and receivers of the primary outputs of a chip are connected to an L1/L2 pair. This methodology calls for loading appropriate binary values into these master-slave latches which will successively turn off all off-chip drivers on every chip on the module except for the chips under test. In this manner, the chip(s) under test may be tested as if it (they) were alone on the module. Thus, by electrically isolating the chip under test from all others, it now becomes possible to reapply the appropriate chip test patterns to it. The ECIPT methodology has thus far been utilized in conjunction with deterministic patterns. (Deterministic patterns are those which are created by assuming the existence of a fault and then selecting a path between input and output which is sensitive to that fault, i.e. sensitizing a path to detect the fault. This term is used in opposition to random patterns which are not associated to any fault in particular). The application of deterministic patterns to a chip under test presupposes the availability of a computer controlled automatic tester. Otherwise, it would not be possible to generate test patterns and measure the necessary responses at the outputs. We have thus explained how ECIPT partitions logic along chip boundaries making it unnecessary to recreate a set of patterns to test a module, since the same chip patterns can now be reused for the module. We have also established that this testing methodology requires: a tester, which is expensive and cumbersome; the generation and handling of a multitude of test patterns, which is time consuming and labor intensive; and the handling of large amounts of test data. The above considerations are fundamental limitations of the ECIPT technique.
Through-The-Pins Testing, as described in the IBM TDB dated July 1980, pages 607-609, by Carpenter et al, has also been used to test multi-chip modules. This technique essentially treats the multi-chip module as if it were a single chip entity. Test patterns are created to detect all possible faults within that package, oftentimes with the help of partitioning techniques, without which test pattern generation would not always be feasible. Testing is done through the module I/O pins as its name indicates it instead of using the I/O's or EC pads of individual chips. However, a tester and its corresponding burden are still required. Moreover, partitioning is inadequate to form partitions along chip boundaries.
In view of the above, neither ECIPT nor Chip-In-Place Testing, nor testing Through-The-Pins techniques completely satisfy the above stated goals specified for testing multi-chip packages. In particular, using ECIPT, some partitioning problems may be solved, but a tester is still required and large amounts of computer memory must be utilized. Using Chip-In-Place testing, a complex mechanical test process is required, adversely affecting the tester throughput. Using Through-The-Pins testing, an inordinate amount of time must be spent generating the required set of test vectors and partitioning and diagnostic problems are prevalent. In any of the above test methods, elaborate VLSI testers must be used just to apply the vectors to the chip and collect the corresponding responses. In addition, testing is time consuming because the vectors have to be serially shifted in and the responses serially shifted out. Thus, as the density of chips increases, so too does the test generation effort. What is needed, therefore, is a method of testing VLSI chip designs that incorporates the advantages of LSSD, but that does not impose the software management and test generation burdens associated therewith.
One method known in the art to reduce the amount of test data that must be stored when a deterministic method is employed, is "signature analysis". (See Frohwerk, Robert A., "Signature Analysis: A New Digital Field Service Method," Hewlett-Packard Journal, May 1977, pp. 2-8.) In normal LSSD testing, the responses from the test vectors must be compared to known good test vectors. Thus, a large catalog of good test vectors must be stored in order to perform such a comparison. In contrast, signature analysis eliminates the need to generate and store such a catalog of good test vectors. Signature analysis recognizes that an inherent "signature" is present in the data streams of output test response vectors. This "signature" can be derived, and if it is still detected as being present in the response vectors, one is assured that a successful or correct response has been given by the circuit under test.
An additional method known in the art to test LSI circuits is VLSI self test or "random testing". (See, e.g., Sedmak, R. M., "Implementation Techniques for Self-Verification", Proceedings of the 1979 IEEE Test Conference, October 1979, pp. 37-41; Koenemann, Bernd, "Built-in Logic Block Observation Techniques", Proceedings of the 1979 IEEE Test Conference, October 1979, pp. 37-41.) Using this approach, there is no need to externally generate and apply test vectors. Rather, the circuits existing within the VLSI chip design, many of which are designed thereinto solely for testing purposes, are used. Input patterns are randomly generated and applied to the inputs of the unit under test. Said input patterns can be generated, among others, by a Linear Feedback Shift Register (LFSR). Such registers generate long, repetitive pseudo-noise sequences, short segments of which display properties similar to random patterns. The responses of the outputs of the unit under test are accumulated in a Multiple Input Shift Register (MISR), and upon applying a determined set of said patterns it becomes possible to obtain the signature of said network. The aforementioned test generation method can be optimized by assigning different weights to the input leads of the unit under test. Significant advantages may be realized with VLSI self test: (1) test vectors can be generated automatically inside the chip at high speed; (2) neither test nor response vectors need to be stored external to the chip; (3) testing can proceed at much higher speed than is normally possible using LSI testers; (4) no expensive VLSI testers are needed.
Unfortunately, prior art VLSI self test techniques also suffer from some disadvantages. Most particularly, it demands extra resources in terms of design time and chip area. Moreover, the package under test has to be partitioned carefully into smaller testable sections and the designer must exercise considerable skill in mating the self test circuits to the rest of his chip. The overall effectiveness of the self test method depends largely on how skillfully this is done. Careless use of selftest features can waste a lot of chip real estate.
The state of the art test methods described above along with the inherent limitations of each are not adequate to isolate, partition test and easily diagnose VLSI chips on multi-chip modules.
A recent advance in the self test art was made in U.S. Pat. No. 4,519,078 granted to D. Komonytsky on May 21, 1985. Komonytsky teaches that it is possible to combine the Design for Testability Technique, known as LSSD (Level Sensitive Scan Design), with self test and thus do away with the tester. Logic on a module can be partitioned along the boundaries set by the shift register latch banks and letting a set of random patterns be created and applied to each partition. These partitions consist of combinatorial logic. The output responses of said partition can be accumulated on the next bank of shift registers, which provides the second boundary of said partition. Thus a complex module containing a large plurality of chips can be reduced to a limited number of partitions, each comprising some combinatorial logic "sandwiched" between two banks of shift registers, or one set of shift registers and the inputs of the package, or one set of shift registers and the outputs of said package.
It is oftentimes found that for certain applications a logic design may not require any sequential (memory) elements in its design. These designs may eventually lead to chip partitions that are devoid of any latches, and as a consequence may not require any LSSD shift register latches. Assuming that the chips are mounted on a second level package, such as a module (multi-chip-module), Komonytsky's approach would require a logic partition that could theoretically encompass a large portion of the module, which could well be beyond the handling capability of the computer to store and simulate logic. In more general terms, because the latches of Komonytsky are integral with system logic, and thus partitions are determined by system logic, Komonytsky's approach does not teach us how to partition logic in components sufficiently small in the absence of memory elements which can take advantages of a structured design such as LSSD. Komonytsky recognizes existing sequential (memory) elements within the logic organized as shift register latches as natural boundaries for his partitions. In the absence of any such shift register latches in a given chip, such a chip would have to be incorporated into a partition and could not stand by itself as a single chip partition. Moreover, sequential elements, organized as shift register latches (i.e. SRLs) usually do not coincide with either the inputs or outputs of a chip, but are located within the internal logic of a given chip. Thus, a partition may encompass not only purely combinatorial chips, but also portions of chips bounded by the aforementioned shift register latches. Furthermore, the partitions created along SRL boundaries may oftentimes overlap because circuitry of many SRL banks may be required to be used by more than one partition.
In sum, the partitions formed by combining LSSD and self test as taught by Komonytsky are not defined by chip boundaries, but rather they encompass either a multitude of chips and portions thereof or merely portions of a chip or chips. In addition, such partitions overlap each other.
The problems associated with testing very large multi-chip packages, such as multilayered ceramic substrate packages typically having greater than 100 interconnected chips, (i.e. "Thermal Conduction Modules" (TCMs), disclosed in the IBM News, Special Edition, November 1980, Copyright by the IBM Corporation (see FIG. 4A for example), clearly demonstrates how many of the aforementioned testing problems come to light. The existence of at least 100 interconnected chips mounted on a ceramic substrate makes self test techniques impractical unless adequate means for partitioning logic into manageable partitions can be found. Self test techniques in the art require a dedicated test chip. On those packages having a relatively small number of large high density chips, the dedication of a chip site for a test chip can be a major detriment to package and system performance. Furthermore, the task of generating an adequate number of sets of test patterns consumes enormous amounts of CPU time, and the storing and handling of the test patterns likewise imposes great demands on any tester.
The aforementioned testing problems exist for any multi-chip packaging structure having large numbers of chips. Another example of such a multi-chip packaging structure is disclosed in patent application Ser. No. 864,228, wherein means are described for packaging VLSI circuit chips on a semiconductor substrate, preferably silicon. The silicon substrate contains thin-film layers of polyimide and wiring that serves as the media to provide the necessary interconnections between the chips. Like other large multichip packages such as TCMs, such a package is inherently difficult to test. However, the method of the present invention may be applied in a novel structural embodiment to test such a package.
In view of the above, there is a need in the art for finely partitioning and testing a multi-chip package without the need of a tester.
A further need exits to be able to electrically partition either a single chip or a group of chips mounted on a multi-chip module, and test the partitioned chip or chips without a tester.
There is a further need in the art to be able to diagnose each chip or group of chips in a multi-chip package by isolating a defective chip so that the chip can be readily replaced, and the package can be rapidly repaired, and put back into operation or initially installed in a system. There is a need to accomplish such diagnosis without requiring an expensive computer driven automatic tester.
There is a further need in the art to significantly reduce the number of test patterns required to test multi-chip packages.
A further need exists to provide a partitioning, testing and diagnosing method and means that does not require a dedicated test chip.
There is also a need in the art for a method and means of partitioning, testing and diagnosing of a semiconductor base substrate multi-chip package.